Translation lookaside buffer (TLB) refers to a hardware cache that stores virtual-physical address translations and is used to improve virtual address translation speed. On a memory access, a TLB lookup is performed to search for the required address translation in the TLB and if the translation is not found, the miss is termed as a TLB miss. However, conventional solutions do not provide an efficient manner of managing TLB misses; for example, one conventional technique provides for a hardware-based walking of pages tables to determine the physical address for the memory access or whether there exists an entry for a specified virtual address. This high latency of hardware-based page walks makes TLB misses expensive and inefficient, which often leads to a significant slowing down of the execution workload, resulting in a slowdown of power and performance.